The subject matter discussed in the background section should not be assumed to be prior art merely as a result of its mention in the background section. Similarly, a problem mentioned in the background section or associated with the subject matter of the background section should not be assumed to have been previously recognized in the prior art. The subject matter in the background section merely represents different approaches, which in and of themselves may also correspond to embodiments of the claimed subject matter.
Today's consumer electronics market frequently demands complex functions requiring very intricate circuitry. Scaling to smaller and smaller fundamental building blocks, (e.g. transistors), has enabled the incorporation of even more intricate circuitry on a single semiconductor device with each progressive generation. Modern semiconductor devices, often referred to as semiconductor packages, now incorporate controllers and entire System on a Chip or (SoC) design methodologies in which there are processing components, memories, Input/Output elements, serial interfaces, and many other functional elements.
For any product lifecycle there needs to be testing conducted to verify the functionality and performance of such devices. It is further necessary to perform testing of the PCIe interfaces and handling of PCIe messaging on the processing component.
Testing however presents serious challenges with respect to high volume manufacturing. Consider for instance that somewhere on the order of 300 million units of a given product will require testing over a product lifecycle which in turn requires thousands of unit testers, arranged into hundreds of test beds.
Two problems immediately present themselves in such a scenario. First, the capital outlay to acquire thousands of high-end graphics cards can be cost prohibitive. Secondly, the physical size and bulk of the PCIe devices, such as the exemplary graphics cards, are relatively large compared to the very compact semiconductor device test beds, thus necessitating a very large physical space to perform such testing, which may not be economically feasible.
Other less intuitive issues also arise with the testing of such semiconductor devices. First is the problem of detecting malicious attacks from hackers. Certain semiconductor devices incorporate protections against malicious attack such as hacking attempts. Counter-intuitively, use of commercially available PCIe devices such as graphics cards will operate according to accepted standards and therefore are not useful for testing the semiconductor device's internal protections against attack.
Another problem is with respect to the volume of messaging. Similar to the issue with hacking attempts and handling of malicious messages, commercially available PCIe devices simply are not capable of overwhelming the semiconductor device with valid, but excessive messages. By design, such semiconductor devices incorporate many protections against flooding and the normal peaks and valleys inherent in device communications. Nonetheless, it may be desirable to test such aspects of the manufactured semiconductor devices to ensure that these flooding and excessive volume message handing protections are operating correctly.
Yet another non-intuitive problem relates to the lack of availability of PCIe and DMI devices which are capable of satisfactorily exercising newly released semiconductor device for the purposes of testing. Because the semiconductor devices themselves are newly released, it has been observed repeatedly that a significant delay may exist before commercially available PCIe and DMI devices are available to the market place as the manufacturers of such PCIe and DMI devices prefer to await the release of the newest version of the semiconductor devices to the market place before supporting such devices. Consider for instance, for the sake of example, a Gen-4 CPU, a latest generation semiconductor device 199 developed and ready for release to the market. Such a device requires testing, however, new generation Gen-4 PCIe devices, such as new Gen-4 graphics cards, will not be available to the marketplace until some time after the release of the latest generation semiconductor device because the new Gen-4 PCIe devices must ensure compliance to the latest protocol, consequently resulting in a type of a chicken and the egg problem.
The present state of the art may therefore benefit from the innovative high speed serial controller testing, may benefit from the implementation of SoC coverage through virtual devices in PCIe and DMI controllers; and may further benefit from the implementation of virtual device observation and debug network for high speed serial IOS as is described herein.